Most of the gate aspirants feel almost helpless about the guidance in their interviews of M.Tech .Even if They Do fairly well in gate, the unknown patterns of interview makes the student confused how to prepare for it. In this context I will be discussing about those interviews which has given me many anxious moments with citing a few examples from my experience in CEDT,IISC and from my few friends which I collected. Many many thanks to them who had contributed by sharing their experiences.
First of all ,be aware of what a interview is all about. What they want to know to take into the particular course or what they should expect from you is what matters. Suppose you have applied for a course of microelectronics. They will ask you about VLSI, solid state devices,HDLs ,because that is the basic knowledge you need to know to work in the particular field. So first tips to interview is to carefully applying into the institutions with a particular choice and prepare for it assuming the topics that are expected from you and go it deeply with a problematic approach. What I mean by problematic approach ,suppose you read a particular topic MosFet and their characteristics ,use etc.Then divide yourself into two, one part playing the role of an imagined interviewer and the other student. Ask yourself question and give answers .Then think what is the next question I can face regarding this going in to a further deep. For instance, they ask you to draw and identify the different regions of mosfet V-I characteristics. What is the next question gonna be? Yah you guess it right. The criteria for saturation and linear region .And then a little bit of their use and the derivation of the criterion. In this way if you approach things ,you will be more confident about a subject .(at least you pretend to be)
MY INTERVIEW EXPERIENCE IN CEDT, IISC:
I was called by IISC by department of CEDT(CENTERE FOR ELECTRONICS DESIGN AND TECHNOLOGY) and SERC(SUPERCOMPUTER EDUCATION AND RESEARCH CENTRE) for an aptitude test and interview (if I get through the aptitude test) for M.tech course In electronics design and computational science. As being a electronics and communication student ,from the very beginning I targeted CEDT, which seems to be the one of the best industry sponsored postgraduate courses in India. The aptitude test was subjective type and had mostly analog circuit based questions and contained a little bit of mathematics, mechanics ,logical reasoning. There were around 300 people, I guess. The test was held on 18th april and the result of the aptitude test was declared on that very day night. Luckily I was one of the 144 people who got selected. My interview was 2 pm next day. I heard that the final year B.tech project was important .So I revised myself with the project with that problematic approach. The interviews was on schedule .Everyone was allotted 20 minutes. I got called on 2.10 pm. I entered the room confidently without letting them know what my mental condition was(you can assume that I guess). They were four professors sitting around a round table .They smiled as I entered the room and told to be comfortable .This really helped and I gained confidence. However as usual they started with my B.tech project. I suitably explained my project .My project was simulation based mosfet scaling, a solid state based project. They went deep into it with details .As they understood I am fully confident about it, first professor started asking me questions about mosfet
· Draw the Vds-Ids characteristics of MosFet.
As I did……
· Explain different regions like saturation,linear,cutoff.
· What is the criteria for saturation?
I answered Vds>=Vgs-Vt. Then…
· Derive it and explain?
· He switched to Digital electronics. He asked me to draw a circuit of an odd parity checker of 8 bit ?.
It was simple enough.3 stage x-or based circuit. Next …
· If the delay of a x-or gate is 5ns ,what is the maximum frequency of input ?
Ans: as the circuit was 3 stage the delay to output from input was 15ns.So max frequency was
1/15ns………then he asked to generalize the concept
· What if the circuit was for N bit input? What should be the delay assuming that x-or delay is same as before?
I took a little time. My problematic approach suggested the no of stage for general N bit should be [ log2N]. So the delay is 5*[ log2N]. the rest is easy .Then he handled me to the next professor.
Q1: can you make a circuit to implement voltage controlled resistance?
Sure I could….i heard it many times in the video lectures of NPTEL that the channel of a mosfet acts a resistance which is controlled by voltage. So I explained with diagram and equations. I didn’t know whether I answered right or wrong .The expression on the proff’s face was so indifferent and cool that even that tension crammed environment of the room ,I could find the resemblance of his face and personality of the Marlin Brando in GODFATHER. He didn’t let the students know what he was thinking…
However the next question was as obvious as the rise of moon after sunset.
Q2:Where is this used or necessary?
I answered this is used to fabricate resistance in ICs. He seemed a bit satisfied. But unfortunately he proved his satisfaction as my illusion. The next question came to me as .9calliber bullet .
Q2.Can u make a digital resistance with the use of diac or triac?
I knew I couldn’t answer this .so without wasting time I surrendered ….
Q3.Then I was asked to draw a non inverting amplifier and derive the gain?
It seemed to me that his holiness was giving compassion to a war beaten hero like Alexander did to puru.I felt happy to fill me in place of puru.I drew the circuit immediately. And derived the gain as (-rf/r1)
Q4.Make it a 100 gain amplifier?
I did with the feedback resistance (rf= 100k) and the other resistance(r1= 1k).
Q5.What will happen if the resistances are replaced by 100M and 1M?
That was a tricky question like a googly.I had to answer it carefully. I took a little time to think the concept of input impedance .At last I came to a conclusion and answered that the input impedance of the OP-AMP was comparable to r1 and this will lead to falling of the signal level in the input port ,so the gain will go down significantly from 100 .I thought the answer had impressed them.Then they asked the opposite as usual
Q6.What will happen if the resistances are replaced by 100 and 1 ohm?
It was easy enough .The Op-Amp could not source /sink the ampere level current that need to flow as a consequence of the above question.
At last I was relieved from GODFATHER…….and handled to third proff…
It seemed that third professor was waiting eagerly for his chance.” I guess you can identify a little bit of hardware “…….And little bit did I identify among them…as I go through the collection of electronics devices and IC’s collected there… no electronics devices seemed to be absent. However unfortunately he asked a basic few like a dip microcontroller, some transistors etc. However there was surprise waiting! He handled me a INTEL p-4 processor and asked me why this is so weighty? First I thought that I hadn’t heard it right. I thought “How the f…k is I suppose to know that?” ..but didn’t surrender . I asked for a little hint like I was in a reality show. However he answered ,the processor is a little quad chip .But what else it need for packaging? I got it then….”i guess sir it is for heat sink”…I could guess it because my laptop went so hot during gaming that I had wished for a heat sink. He seemed pleased by answer and asked me to tell a few heat sinking material name. It was easy enough. Aluminum was the most widely used .Then the last question of the that 25 minutes interview appeared with a scientific perspective.
“ Can We use some other material instead of aluminum to reduce the weight”…..i was puzzled…..he gave clue .”what about carbon,it has high thermo electricity”…he asked with optimism and expectation. I thought agreeing with him may be a symbol of weakness and lack of independent thinking. So I resisted by arguing with him that carbon is not a metal and can’t be used in packaging. That‘s the end. They relieved me to the free air again…..at least I was free to prepare for the next interview in IIT-B.
Guess you have enjoyed my experience, as I did. Now I present to you some example interview details collected by me.
Questions asked at IISc:
Most of the questions were based on my BE project like why did I select the specific components, what if I change it with something else etc. Apart from that, they gave me 2 components, a relay and a choke and asked me to identify that, asked their characteristics, their usage etc.
Questions asked at IITB:
I was seeking admission in microelectronics. The questions were
- Draw and explain Diode characteristics. Then they added a resistor in series with the diode and asked me to draw and compare the new characteristics with the old one.
- Few questions on OPAMP integrator.
(contributed by shrutee kamat )
- choose the preferences according to your strengths
- interview professors(2 per panel) were young, intelligent.
- nothing related to projects n all.
- i was asked abt CMOS and NAND gate using CMOS.
- single day process
- nothing related to projects
- asked abt favourite subjects (DSP,Op-amps,Digital)
- FSM questions, counters and all in Digital circuits (No. of states reqd, design using JK FF etc)
- in dsp , freq spectrum of the flip-flop o/p wen input is clock
- 1 professor only, (no attitude.. jolly)
IIT-D, VDTT(1st round only)
- 1 professor, aged, ex-VDTT head
- askd a lot about project
- Processor design questions (cache n bus)
- DSP questions on DFT, FFT
- asked to prove FFT complexity (N*logN/2) (A Data structure question- didnt knw the answer)
- Not askd anything further
(contributed by Alap patel )